1. Field of the Invention
This invention relates generally to the processing of digital logic signals and, more particularly, to circuits which provide a comparison between the results of a logic operation and a preselected result.
2. Description of the Related Art
A logic operation on two binary signal operands, such as addition, because of the propagation of the carry signal along a sequence of result binary digits, can be a relatively lengthy operation. Recently, Bosshart et al., in U.S. Pat. No. 5,270,955, issued on Dec. 14, 1993, and assigned to the assignee of the present Application, have disclosed fast compare units which permit comparison of the result, R, of an arithmetic or logical computation on a first operand A and a second operand B to a specified result, S, prior to the completion of the propagation of a carry bit, where A, B, R, and S are N binary bit numbers, and N represents the total number of bits per operand. It will be convenient to refer to the "n.sup.th " bit where n is an index variable whose value extends from 0 to N-1 of the N length binary numbers. The comparison is performed on all bits in parallel, where the comparison performed at the n.sup.th bit can be one of
______________________________________ 1. R.sub.n = 1 when R.sub.n-1 = 1 (1,1) 2. R.sub.n = 1 when R.sub.n-1 = 0 (1,0) 3. R.sub.n = 0 when R.sub.n-1 = 1 (0,1) or 4. R.sub.n = 1 when R.sub.n-1 = 0 (0,0) ______________________________________
Block diagrams for circuits for each of these possible (R.sub.n, R.sub.n-1) results, according to the Bosshart, are shown in FIG. 1a, FIG. 1b, FIG. 1c, and FIG. 1d, respectively. Each of the four circuits includes K/G/P (Kill/Generate/Propagate) generator unit 11.sub.n and K/G/P generator unit 11.sub.n-1. The circuits of FIGS. 1a and 1d include an exclusive OR logic gate 12.sub.n, while the circuits of FIGS. 1b and 1c include an exclusive NOR logic gate 13.sub.n. Each K/G/P generator unit 11.sub.n has the A.sub.n and B.sub.n bit signals from operands A and B applied thereto, while the K/G/P generator unit 11.sub.n-1 has the A.sub.n-1 and B.sub.n-1 bit signals from operands A and B applied thereto. The output signals of the K/G/P generator unit 11.sub.n are the K.sub.n (Kill) signal, the G.sub.n (Generate) signal, and the P.sub.n (Propagate) signal. The output signals of the K/G/P generator unit 11.sub.n-1 are the K.sub.n-1 (Kill) signal, the G.sub.n-1 (Generate) signal, and the P.sub.n-1 (Propagate) signal. In FIG. 1a in which the fast compare unit 15 implements the (0,0) relationship, the P.sub.n and the K.sub.n-1 signals are applied to the input terminals of exclusive OR logic gate 12.sub.n. In FIG. 1b in which the fast compare unit 16 implements the (0,1) relationship, the P.sub.n and the G.sub.n-1 signals are applied to input terminals of exclusive NOR logic gate 13.sub.n. In FIG. 1c in which the fast compare unit 17 implements the (1,0) relationship, the P.sub.n and the K.sub.n-1 signals are applied to input terminals of exclusive NOR logic gate 13.sub.n. In FIG. 1d in which the fast compare unit 18 implements the (1,1) relationship, P.sub.n and the G.sub.n-1 signals are applied to input terminals of exclusive OR logic gate 12.sub.n. The Bosshart reference refers to the output of the bit comparator as the one-bit-zero signal Z.sub.n. The Z.sub.n signal will be a "1" when the associated (R.sub.n, R.sub.n-1) conditions are present. Otherwise, the Z.sub.n signal will be "0", when the associated conditions are not present. The n.sup.th one-bit-zero signal is preferably dependent only upon the nth and (n-1).sup.th bit of each operand. The least significant (0.sup.th) bit is dependent only on the 0.sup.th bit of each operand and a (possible) carry-in signal, C.sub.in, because the (n-1).sup.th bit is not available to the least significant one-bit-zero detector. The N one-bit-zero signals are combined to give a total compare signal Z.sub.TOTAL. If the results of all of the N bit comparisons are true (i.e., R.sub.n =S.sub.n if R.sub.n-1 =S.sub.n-1 for all n from 1 to N-1 and R.sub.0 =S.sub.0, then R=S, i.e., the result R of the operation is equal to the specified number S.
In the prior art, circuits could be constructed to do a fast comparison of the result R of a logic operation to any predetermined specified number S. Circuits could also be constructed to compare predetermined subfield of a result R to a predetermined specified subfield of S, when combined with a full calculation of the result bits of lower significance than the subfield. However, the need to provide a separate array of circuits for each result R or subfield of R has heretofore limited the usefulness of the fast compare apparatus disclosed by Bosshart.
A need has therefore been felt for a programmable fast compare apparatus wherein a result number R can be compared with a specified number S, the specified number S being progammable. This fast compare apparatus provides a flexibility with respect to the specified number S, a flexibility not found in the prior art. In addition, a need has been felt to provide programmable fast compare apparatus requiring as few implementing components as possible. A need has also been felt for a fast compare of subfield of the specified number S which is independent of the full calculation of remaining bits positions.